1. Field of the Invention
This invention relates in general to the fabrication of integrated circuit devices, and more particularly to a process for fabricating MOS devices having a recessed gate, improved isolation between gate to source/drain and capacitance reduction of parasitic capacitors between the gate layer and the source/drain regions.
2. Description of the Prior Art
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are widely used semiconductor devices. They can be utilized as switches, amplifiers, or memory devices. However, in the conventional process for fabricating the MOSFET, a gate structure including a gate oxide layer and a gate electrode is formed on the surface of a silicon substrate, which leads to a non-flat surface. As the size of these devices becomes smaller and smaller, it becomes increasingly difficult to perform fabrication photolithography procedures on such non-flat substrate surfaces.
Therefore, a recessed gate MOS device is proposed which overcomes the non-flat surface problem. A prior art process for fabricating such a recessed gate MOS device is described with reference to FIG. 1 as follows. First, a field oxide 11 is formed on silicon substrate 10 by a conventional isolation technique, such as a LOCal Oxidation of Silicon (LOCOS) process, to define the active area. A portion of silicon substrate 10 within the active area is etched, for example, by reactive ion etching (RIE), to form a trench. Next, gate oxide layer 12 is formed by either thermal oxidation or chemical vapor deposition (CVD) to cover the bottom and the side walls of the trench. Polysilicon gate layer 13 is formed on gate oxide layer 12 within the trench by CVD and RIE processes. Thus, a recessed gate structure including gate oxide layer 12 and polysilicon gate layer 13 is formed in the trench resulting in a flat surface. Finally, the prior art device is completed by implanting N type impurities, such as arsenic ions, into silicon substrate 10 to form N.sup.+ source/drain regions 14 that are spaced apart and adjacent to the side walls of the trench. To gain a higher conductivity, titanium silicide (TiSi.sub.2) layer 15 is formed on the surfaces of the gate layer 13 and the N.sup.+ source/drain regions 14 by first sputtering a titanium layer and then performing a rapid thermal anneal (RTA) process, which is well known in the art.
However, the prior art process for fabricating recessed gate MOS devices suffers from the following drawbacks:
(1) Gate oxide layer 12 is formed along the bottom and the side walls of the trench. Thus, corner areas I of gate oxide layer 12 are easily broken down due to the point discharge.
(2) Since a portion of gate oxide layer 12 is sandwiched by the polysilicon gate layer 13 and N.sup.+ source/drain regions 14, parasitic capacitors are formed at positions II that decrease the speed of the device operation.
(3) N.sup.+ source/drain regions 14 and polysilicon gate layer 13 are isolated only by thin gate oxide layer 12. After the formation of titanium silicide 15, surface leakage will occur at positions III that reduce the reliability of the device.